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LIS302DL
MEMS motion sensor 3-axis - 2g/8g smart digital output "piccolo" accelerometer
Preliminary Data
Feature

2.16V to 3.6V supply voltage 1.8V compatible IOs <1mW power consumption 2g/8g dynamically selectable Full-Scale I2C/SPI digital output interface Programmable multiple interrupt generator Embedded high pass filter Embedded self test 10000g high shock survivability ECOPACK(R) RoHS and "Green" compliant (see Section 8) A self-test capability allows the user to check the functioning of the sensor in the final application. The device may be configured to generate inertial wake-up/free-fall interrupt signals when a programmable acceleration threshold is crossed at least in one of the three axes. Thresholds and timing of interrupt generators are completely programmable by the end user on the fly. The LIS302DL is available in plastic Thin Land Grid Array package (TLGA) and it is guaranteed to operate over an extended temperature range from -40C to +85C. The LIS302DL belongs to a family of products suitable for a variety of applications: - - - - Free-Fall detection Motion activated functions Gaming and Virtual Reality input devices Vibration Monitoring and Compensation
LGA-14 (3x5x0.9mm)
Description
The LIS302DL is an ultra compact low-power three axes linear accelerometer. It includes a sensing element and an IC interface able to provide the measured acceleration to the external world through I2C/SPI serial interface. The sensing element, capable of detecting the acceleration, is manufactured using a dedicated process developed by ST to produce inertial sensors and actuators in silicon. The IC interface is manufactured using a CMOS process that allows to design a dedicated circuit which is trimmed to better match the sensing element characteristics. The LIS302DL has dynamically user selectable full scales of 2g/8g and it is capable of measuring accelerations with an output data rate of 100Hz or 400Hz.
Order codes
Part number LIS302DL LIS302DLTR Temp range, C -40 to +85 -40 to +85 Package LGA LGA Packing Tray Tape and reel
October 2006
Rev 1
1/29
www.st.com 29
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Contents
LIS302DL
Contents
1 Block diagram & pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.1 1.2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
Mechanical and electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1 2.2 2.3 2.4 Mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.4.1 2.4.2 2.4.3 Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Zero-g level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Self Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3
Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1 3.2 3.3 Sensing element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 IC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Factory calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4
Application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.1 Soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5
Digital Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.1 5.2 I2C Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.1.1 I2C operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
SPI bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.2.1 5.2.2 5.2.3 SPI Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 SPI Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 SPI Read in 3-wires mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6 7
Register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.1 WHO_AM_I (0Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
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LIS302DL
Contents
7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 7.14 7.15 7.16 7.17
CTRL_REG1 (20h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 CTRL_REG2 (21h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 CTRL_REG3 [Interrupt CTRL register] (22h) . . . . . . . . . . . . . . . . . . . . . . 21 HP_FILTER_RESET (23h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 STATUS_REG (27h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 OUT_X (29h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 OUT_Y (2Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 OUT_Z (2Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 FF_WU_CFG_1 (30h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 FF_WU_SRC_1 (31h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 FF_WU_THS_1 (32h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 FF_WU_DURATION_1 (33h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 FF_WU_CFG_2 (34h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 FF_WU_SRC_2 (35h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 FF_WU_THS_2 (36h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 FF_WU_DURATION_2 (37h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
8 9
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
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Block diagram & pin description
LIS302DL
1
1.1
Figure 1.
Block diagram & pin description
Block diagram
Block Diagram
X+ Y+ Z+
CHARGE AMPLIFIER
MUX A/D CONVERTER CONTROL LOGIC
CS I2C SPI SCL/SPC SDA/SDO/SDI SDO
a
ZYX-
SELF TEST
REFERENCE
TRIMMING CIRCUITS
CLOCK
CONTROL LOGIC
&
INT 1 INT 2
INTERRUPT GEN.
1.2
Pin description
Figure 2. Pin connection
Z Y
1
X
1
6
6 8
13
13
8
TOP VIEW
BOTTOM VIEW
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LIS302DL Table 1.
Pin# 1 2 3 4 5 6 7 8 9 10 11 12
Block diagram & pin description Pin description
Name Vdd_IO GND Reserved GND GND Vdd CS INT 1 INT 2 GND Reserved SDO SDA SDI SDO SCL SPC Power supply for I/O pins 0V supply Connect to Vdd 0V supply 0V supply Power supply SPI enable I2C/SPI mode selection (1: I2C mode; 0: SPI enabled) Inertial interrupt 1 Inertial interrupt 2 0V supply Connect to Gnd SPI Serial Data Output I2C less significant bit of the device address I2C Serial Data (SDA) SPI Serial Data Input (SDI) 3-wire Interface Serial Data Output (SDO) I2C Serial Clock (SCL) SPI Serial Port Clock (SPC) Function
13
14
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Mechanical and electrical specifications
LIS302DL
2
2.1
Table 2.
Symbol FS
Mechanical and electrical specifications
Mechanical characteristics
Mechanical Characteristics(1) (All the parameters are specified @ Vdd=2.5V, T = 25C unless otherwise noted)
Parameter Measurement range(3) Test conditions FS bit set to 0 FS bit set to 1 FS bit set to 0 FS bit set to 1 FS bit set to 0 FS bit set to 0 FS bit set to 1 Max delta from 25C FS bit set to 0 STP bit used X axis Vdd=2.16V to 3.6V Self Test Output Change(6),(7),(8) FS bit set to 0 STP bit used Y axis Vdd=2.16V to 3.6V FS bit set to 0 STP bit used Z axis Vdd=2.16V to 3.6V BW Top Wh System Bandwidth(9) Operating Temperature Range Product Weight -40 30 Min. 2.0 8.0 16.2 64.8 Typ.(2) 2.3 9.2 18 72 0.01 40 60 0.5 19.8 79.2 Max. Unit g
So TCSO TyOff TCOff
Sensitivity Sensitivity Change Vs Temperature Typical Zero-g Level Offset Accuracy(4),(5) Zero-g Level Change Vs Temperature
mg/digit %/C mg mg mg/C
-16
-3
LSb
Vst
3
16
LSb
3
16
LSb
ODR/2 +85
Hz C mgram
1. The product is factory calibrated at 2.5V. The device can be used from 2.16V to 3.6V 2. Typical specification are not guaranteed 3. Verified by wafer level test and measurement of initial offset and sensitivity 4. Typical zero-g level offset value after MSL3 preconditioning 5. Offset can be eliminated by enabling the built-in high pass filter 6. If STM bit is used values change in sign for all axes 7. Self Test output changes with the power supply. Self test "output change" is defined as OUTPUT[LSb](Self-test bit on ctrl_reg1=1) -OUTPUT[LSb](Self-test bit on ctrl_reg1=0). 1LSb=4.6g/256 at 8bit representation, 2.3g Full-Scale 8. Output data reach 99% of final value after 3/ODR when enabling Self-Test mode due to device filtering 9. ODR is output data rate. Refer to table 3 for specifications
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LIS302DL
Mechanical and electrical specifications
2.2
Table 3.
Symbol Vdd Vdd_IO Idd IddPdn VIH VIL VOH VOL
Electrical characteristics
Electrical Characteristics(1) (All the parameters are specified @ Vdd=2.5V, T= 25C unless otherwise noted)
Parameter Supply voltage I/O pins Supply voltage(3) Supply current Current consumption in power-down mode Digital High level Input voltage Digital Low level Input voltage High level Output Voltage Low level Output Voltage DR=0 100 Hz DR=1 400 ODR/2 3/ODR -40 +85 Hz s 0.9*Vdd _IO 0.1*Vdd _IO T = 25C, ODR=100Hz T = 25C 0.8*Vdd _IO 0.2*Vdd _IO Test conditions Min. 2.16 1.71 0.3 1 Typ.(2) 2.5 Max. 3.6 Vdd+0.1 0.4 5 Unit V V mA A V V V V
ODR BW Ton Top
Output Data Rate System Bandwidth(4) Turn-on Time(5)
Operating Temperature Range
C
1. The product is factory calibrated at 2.5V. The device can be used from 2.16V to 3.6V 2. Typical specification are not guaranteed 3. It is possible to remove Vdd maintaining Vdd_IO without blocking the communication busses, in this condition the measurement chain is powered off. 4. Filter cut-off frequency 5. Time to obtain valid data after exiting Power-Down mode
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Mechanical and electrical specifications
LIS302DL
2.3
Absolute maximum ratings
Stresses above those listed as "absolute maximum ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 4.
Symbol Vdd Vdd_IO Vin Supply voltage I/O pins Supply voltage Input voltage on any control pin (CS, SCL/SPC, SDA/SDI/SDO) Acceleration (Any axis, Powered, Vdd=2.5V) 10000g for 0.1 ms 3000g for 0.5 ms AUNP TOP TSTG ESD Acceleration (Any axis, Unpowered) 10000g for 0.1 ms Operating Temperature Range Storage Temperature Range Electrostatic discharge protection -40 to +85 -40 to +125 0 - 2 (HBM) C C kV
Absolute maximum ratings
Ratings Maximum Value -0.3 to 6 -0.3 to 6 -0.3 to Vdd_IO +0.3 3000g for 0.5 ms Unit V V V
APOW
Note:
Supply voltage on any pin should never exceed 6.0V This is a Mechanical Shock sensitive device, improper handling can cause permanent damages to the part This is an ESD sensitive device, improper handling can cause permanent damages to the part
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LIS302DL
Mechanical and electrical specifications
2.4
2.4.1
Terminology
Sensitivity
Sensitivity describes the gain of the sensor and can be determined e.g. by applying 1g acceleration to it. As the sensor can measure DC accelerations this can be done easily by pointing the axis of interest towards the center of the earth, noting the output value, rotating the sensor by 180 degrees (point to the sky) and noting the output value again. By doing so, 1g acceleration is applied to the sensor. Subtracting the larger output value from the smaller one and dividing the result by 2 leads to the actual sensitivity of the sensor. This value changes very little over temperature and also very little over time. The Sensitivity Tolerance describes the range of Sensitivities of a large population of sensor.
2.4.2
Zero-g level
Zero-g level Offset (Off) describes the deviation of an actual output signal from the ideal output signal if there is no acceleration present. A sensor in a steady state on a horizontal surface will measure 0g in X axis and 0g in Y axis whereas the Z axis will measure 1g. The output is ideally in the middle of the dynamic range of the sensor (content of OUT registers 00h, data expressed as 2's complement number). A deviation from ideal value in this case is called Zero-g offset. Offset is to some extent a result of stress to a precise MEMS sensor and therefore the offset can slightly change after mounting the sensor onto a printed circuit board or exposing it to extensive mechanical stress. Offset changes little over temperature, see "Zero-g level change vs. temperature". The Zero-g level of an individual sensor is stable over lifetime. The Zero-g level tolerance describes the range of Zero-g levels of a population of sensors.
2.4.3
Self Test
Self Test allows to check the sensor functionality without moving it. The Self Test function is off when the self-test bit of ctrl_reg1 (control register 1) is programmed to `0`. When the selftest bit of ctrl_reg1 is programmed to `1` an actuation force is applied to the sensor, simulating a definite input acceleration. In this case the sensor outputs will exhibit a change in their DC levels which is related to the selected full scale through the device sensitivity. When Self Test is activated, the device output level is given by the algebraic sum of the signals produced by the acceleration acting on the sensor and by the electrostatic test-force. If the output signals change within the amplitude specified inside Table 2, than the sensor is working properly and the parameters of the interface chip are within the defined specification.
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Functionality
LIS302DL
3
Functionality
The LIS302DL is a ultracompatct, low-power, digital output 3-axis linear accelerometer packaged in a LGA package. The complete device includes a sensing element and an IC interface able to take the information from the sensing element and to provide a signal to the external world through an I2C/SPI serial interface.
3.1
Sensing element
A proprietary process is used to create a surface micro-machined accelerometer. The technology allows to carry out suspended silicon structures which are attached to the substrate in a few points called anchors and are free to move in the direction of the sensed acceleration. To be compatible with the traditional packaging techniques a cap is placed on top of the sensing element to avoid blocking the moving parts during the moulding phase of the plastic encapsulation. When an acceleration is applied to the sensor the proof mass displaces from its nominal position, causing an imbalance in the capacitive half-bridge. This imbalance is measured using charge integration in response to a voltage pulse applied to the sense capacitor. At steady state the nominal value of the capacitors are few pF and when an acceleration is applied the maximum variation of the capacitive load is in fF range.
3.2
IC interface
The complete measurement chain is composed by a low-noise capacitive amplifier which converts into an analog voltage the capacitive unbalancing of the MEMS sensor and by analog-to-digital converters. The acceleration data may be accessed through an I2C/SPI interface thus making the device particularly suitable for direct interfacing with a microcontroller. The LIS302DL features a Data-Ready signal (RDY) which indicates when a new set of measured acceleration data is available thus simplifying data synchronization in digital system employing the device itself. The LIS302DL may also be configured to generate an inertial Wake-Up and Free-Fall interrupt signal accordingly to a programmed acceleration event along the enabled axes. Both Free-Fall and Wake-Up can be available simultaneously on two different pins.
3.3
Factory calibration
The IC interface is factory calibrated for sensitivity (So) and Zero-g level (Off). The trimming values are stored inside the device by a non volatile structure. Any time the device is turned on, the trimming parameters are downloaded into the registers to be employed during the normal operation. This allows the user to employ the device without further calibration.
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LIS302DL
Application hints
4
Application hints
Figure 3. LIS302DL electrical connection
Vdd Vdd_IO
6
1
Y
Z
1
X
10uF
Top VIEW
6 8
13
100nF
8
13
TOP VIEW
SDA/SDI/SDO
DIRECTION OF THE DETECTABLE ACCELERATIONS
SCL/SPC
INT_1
INT_2
GND
Digital signal from/to signal controller.Signal's levels are defined by proper selection of Vdd_IO
The device core is supplied through Vdd line while the I/O pads are supplied through Vdd_IO line. Power supply decoupling capacitors (100 nF ceramic, 10 F Al) should be placed as near as possible to the pin 6 of the device (common design practice). All the voltage and ground supplies must be present at the same time to have proper behavior of the IC (refer to Fig. 3). It is possible to remove Vdd maintaining Vdd_IO without blocking the communication busses, in this condition the measurement chain is powered off. The functionality of the device and the measured acceleration data is selectable and accessible through the I2C/SPI interface.When using the I2C, CS must be tied high while SDO must be left floating. The functions, the threshold an the timing of the two interrupt pins (INT 1 and INT 2) can be completely programmed by the user though the I2C/SPI interface.
4.1
Soldering information
The LGA package is compliant with the ECOPACK, RoHS and "green" standard. It is qualified for soldering heat resistance according to JEDEC J-STD-020C. Pin #1 indicator is electrically connected to pin 1. Leave pin 1 indicator unconnected during soldering. Land pattern and soldering recommendation are available at www.st.com/mems.
SDO
CS
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Digital Interfaces
LIS302DL
5
Digital Interfaces
The registers embedded inside the LIS302DL may be accessed through both the I2C and SPI serial interfaces. The latter may be SW configured to operate either in 3-wire or 4-wire interface mode. The serial interfaces are mapped onto the same pads. To select/exploit the I2C interface, CS line must be tied high (i.e connected to Vdd_IO). Table 5. Serial interface pin description
PIN Description SPI enable I2C/SPI mode selection (1: I2C mode; 0: SPI enabled) I2C Serial Clock (SCL) SPI Serial Port Clock (SPC) I2C Serial Data (SDA) SPI Serial Data Input (SDI) 3-wire Interface Serial Data Output (SDO) SPI Serial Data Output (SDO)
PIN Name CS SCL/SPC
SDA/SDI/SDO SDO
5.1
I2C Serial Interface
The LIS302DL I2C is a bus slave. The I2C is employed to write the data into the registers whose content can also be read back. The relevant I2C terminology is given in the table below. Table 6.
Term Transmitter Receiver Master Slave
Serial interface pin description
Description The device which sends data to the bus The device which receives data from the bus The device which initiates a transfer, generates clock signals and terminates a transfer The device addressed by the master
There are two signals associated with the I2C bus: the Serial Clock Line (SCL) and the Serial DAta line (SDA). The latter is a bidirectional line used for sending and receiving the data to/from the interface. Both the lines are connected to Vdd_IO through a pull-up resistor embedded inside the LIS302DL. When the bus is free both the lines are high. The I2C interface is compliant with Fast Mode (400 kHz) I2C standards as well as the Normal Mode.
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LIS302DL
Digital Interfaces
5.1.1
I2C operation
The transaction on the bus is started through a START (ST) signal. A START condition is defined as a HIGH to LOW transition on the data line while the SCL line is held HIGH. After this has been transmitted by the Master, the bus is considered busy. The next byte of data transmitted after the start condition contains the address of the slave in the first 7 bits and the eighth bit tells whether the Master is receiving data from the slave or transmitting data to the slave. When an address is sent, each device in the system compares the first seven bits after a start condition with its address. If they match, the device considers itself addressed by the Master. The Slave ADdress (SAD) associated to the LIS302DL is 001110xb. SDO pad can be used to modify less significant bit of the device address. If SDO pad is connected to voltage supply LSb is `1' (address 0011101b) else if SDO pad is connected to ground LSb value is `0' (address 0011100b). This solution permits to connect and address two different accelerometer to the same I2C lines. Data transfer with acknowledge is mandatory. The transmitter must release the SDA line during the acknowledge pulse. The receiver must then pull the data line LOW so that it remains stable low during the HIGH period of the acknowledge clock pulse. A receiver which has been addressed is obliged to generate an acknowledge after each byte of data has been received. The I2C embedded inside the LIS302DL behaves like a slave device and the following protocol must be adhered to. After the start condition (ST) a salve address is sent, once a slave acknowledge (SAK) has been returned, a 8-bit sub-address will be transmitted: the 7 LSb represent the actual register address while the MSB enables address auto increment. If the MSb of the SUB field is 1, the SUB (register address) will be automatically incremented to allow multiple data read/write. The slave address is completed with a Read/Write bit. If the bit was `1' (Read), a repeated START (SR) condition will have to be issued after the two sub-address bytes; if the bit is `0' (Write) the Master will transmit to the slave with direction unchanged. Transfer when Master is writing one byte to slave
Master Slave ST SAD + W SAK SUB SAK DATA SAK SP
Transfer when Master is writing multiple bytes to slave:
Master Slave ST SAD + W SAK SUB SAK DATA SAK DATA SAK SP
Transfer when Master is receiving (reading) one byte of data from slave:
Master Slave ST SAD + W SAK SUB SAK SR SAD + R SAK DATA NMAK SP
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Digital Interfaces Transfer when Master is receiving (reading) multiple bytes of data from slave
Master Slave Master Slave DATA ST SAD + W SAK MAK DATA SUB SAK SR SAD + R SAK NMAK DATA
LIS302DL
MAK
SP
Data are transmitted in byte format (DATA). Each data transfer contains 8 bits. The number of bytes transferred per transfer is unlimited. Data is transferred with the Most Significant bit (MSb) first. If a receiver can't receive another complete byte of data until it has performed some other function, it can hold the clock line, SCL LOW to force the transmitter into a wait state. Data transfer only continues when the receiver is ready for another byte and releases the data line. If a slave receiver doesn't acknowledge the slave address (i.e. it is not able to receive because it is performing some real time function) the data line must be left HIGH by the slave. The Master can then abort the transfer. A LOW to HIGH transition on the SDA line while the SCL line is HIGH is defined as a STOP condition. Each data transfer must be terminated by the generation of a STOP (SP) condition. In order to read multiple bytes, it is necessary to assert the most significant bit of the subaddress field. In other words, SUB(7) must be equal to 1 while SUB(6-0) represents the address of first register to read. In the presented communication format MAK is Master Acknowledge and NMAK is No Master Acknowledge.
5.2
SPI bus interface
The LIS302DL SPI is a bus slave. The SPI allows to write and read the registers of the device. The Serial Interface interacts with the outside world with 4 wires: CS, SPC, SDI and SDO. Figure 4.
CS SPC SDI
RW MS AD5 AD4 AD3 AD2 AD1 AD0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
Read & write protocol
SDO
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
CS is the Serial Port Enable and it is controlled by the SPI master. It goes low at the start of the transmission and goes back high at the end. SPC is the Serial Port Clock and it is controlled by the SPI master. It is stopped high when CS is high (no transmission). SDI and SDO are respectively the Serial Port Data Input and Output. Those lines are driven at the falling edge of SPC and should be captured at the rising edge of SPC.
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LIS302DL
Digital Interfaces Both the Read Register and Write Register commands are completed in 16 clock pulses or in multiple of 8 in case of multiple byte read/write. Bit duration is the time between two falling edges of SPC. The first bit (bit 0) starts at the first falling edge of SPC after the falling edge of CS while the last bit (bit 15, bit 23, ...) starts at the last falling edge of SPC just before the rising edge of CS.
bit 0: RW bit. When 0, the data DI(7:0) is written into the device. When 1, the data DO(7:0) from the device is read. In latter case, the chip will drive SDO at the start of bit 8. bit 1: MS bit. When 0, the address will remain unchanged in multiple read/write commands. When 1, the address will be auto incremented in multiple read/write commands. bit 2-7: address AD(5:0). This is the address field of the indexed register. bit 8-15: data DI(7:0) (write mode). This is the data that will be written into the device (MSb first). bit 8-15: data DO(7:0) (read mode). This is the data that will be read from the device (MSb first). In multiple read/write commands further blocks of 8 clock periods will be added. When MS bit is 0 the address used to read/write data remains the same for every block. When MS bit is 1 the address used to read/write data is incremented at every block. The function and the behavior of SDI and SDO remain unchanged.
5.2.1
SPI Read
Figure 5. SPI Read protocol
CS SPC SDI
RW MS AD5 AD4 AD3 AD2 AD1 AD0
SDO
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
The SPI Read command is performed with 16 clock pulses. Multiple byte read command is performed adding blocks of 8 clock pulses at the previous one.
bit 0: READ bit. The value is 1. bit 1: MS bit. When 0 do not increment address, when 1 increment address in multiple reading. bit 2-7: address AD(5:0). This is the address field of the indexed register. bit 8-15: data DO(7:0) (read mode). This is the data that will be read from the device (MSb first). bit 16-... : data DO(...-8). Further data in multiple byte reading.
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Digital Interfaces Figure 6.
CS SPC SDI
RW MS AD5 AD4 AD3 AD2 AD1 AD0
LIS302DL Multiple bytes SPI Read Protocol (2 bytes example)
SDO
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 DO15 DO14 DO13 DO12 DO11 DO10 DO9 DO8
5.2.2
SPI Write
Figure 7.
CS SPC SDI
RW MS AD5 AD4 AD3 AD2 AD1 AD0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
SPI Write protocol
The SPI Write command is performed with 16 clock pulses. Multiple byte write command is performed adding blocks of 8 clock pulses at the previous one. bit 0: WRITE bit. The value is 0. bit 1: MS bit. When 0 do not increment address, when 1 increment address in multiple writing. bit 2 -7: address AD(5:0). This is the address field of the indexed register. bit 8-15: data DI(7:0) (write mode). This is the data that will be written inside the device (MSb first). bit 16-... : data DI(...-8). Further data in multiple byte writing. Figure 8.
CS SPC SDI
RW MS AD5 AD4 AD3 AD2 AD1 AD0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DI15 DI14 DI13 DI12 DI11 DI10 DI9 DI8
Multiple bytes SPI Write Protocol (2 bytes example)
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LIS302DL
Digital Interfaces
5.2.3
SPI Read in 3-wires mode
3-wires mode is entered by setting to 1 bit SIM (SPI Serial Interface Mode selection) in CTRL_REG2. Figure 9.
CS SPC SDI/O
RW MS AD5 AD4 AD3 AD2 AD1 AD0 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
SPI Read protocol in 3-wires mode
The SPI Read command is performed with 16 clock pulses: bit 0: READ bit. The value is 1. bit 1: MS bit. When 0 do not increment address, when 1 increment address in multiple reading. bit 2-7: address AD(5:0). This is the address field of the indexed register. bit 8-15: data DO(7:0) (read mode). This is the data that will be read from the device (MSb first). Multiple read command is also available in 3-wires mode.
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Register mapping
LIS302DL
6
Register mapping
The table given below provides a listing of the 8 bit registers embedded in the device and the related address: Table 7. Register address map
Register Address Name Reserved (Do not modify) Who_Am_I Reserved (Do not modify) Ctrl_Reg1 Ctrl_Reg2 Ctrl_Reg3 HP_filter_reset Reserved (Do not modify) Status_Reg -OutX -OutY -OutZ Reserved (Do not modify) FF_WU_CFG_1 FF_WU_SRC_1(ack1) FF_WU_THS_1 FF_WU_DURATION_1 FF_WU_CFG_2 FF_WU_SRC_2 (ack2) FF_WU_THS_2 FF_WU_DURATION_2 Reserved (Do not modify) rw r rw rw rw r rw rw rw r r r r r r r rw rw rw r r Type 0Hex 00-0E 0F 10-1F 20 21 22 23 24-26 27 28 29 2A 2B 2C 2D 2E-2F 30 31 32 33 34 35 36 37 38-3F 011 0000 00000000 011 0001 00000000 011 0010 00000000 011 0011 00000000 011 0100 00000000 011 0101 00000000 011 0110 00000000 011 0111 00000000 Reserved 010 0111 00000000 010 1000 010 1001 010 1010 010 1011 010 1100 010 1101 output Reserved output Not Used output Not Used Not Used 010 0000 00000111 010 0001 00000000 010 0010 00000000 010 0011 dummy Dummy register Reserved 000 1111 00111011 0Binary Reserved Dummy register Reserved Default Comment
Registers marked as reserved must not be changed. The writing to those registers may cause permanent damages to the device. The content of the registers that are loaded at boot should not be changed. They contain the factory calibration values. Their content is automatically restored when the device is powered-up.
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LIS302DL
Register description
7
Register description
The device contains a set of registers which are used to control its behavior and to retrieve acceleration data. The registers address, made of 7 bits, is used to identify them and to write the data through serial interface.
7.1
WHO_AM_I (0Fh)
0 0 1 1 1 0 1 1
Device identification register. This register contains the device identifier that for LIS302DL is set to 3Bh.
7.2
CTRL_REG1 (20h)
DR DR PD FS STP, STM Zen Yen Xen PD FS STP STM Zen Yen Xen
Data rate selection. Default value: 0 (0: 100 Hz output data rate; 1: 400 Hz output data rate) Power Down Control. Default value: 0 (0: power down mode; 1: active mode) Full Scale selection. Default value: 0 (refer to table 2 for typical full scale value) Self Test Enable. Default value: 0 (0: normal mode; 1: self test P, M enabled) Z axis enable. Default value: 1 (0: Z axis disabled; 1: Z axis enabled) Y axis enable. Default value: 1 (0: Y axis disabled; 1: Y axis enabled) X axis enable. Default value: 1 (0: X axis disabled; 1: X axis enabled)
DR bit allows to select the data rate at which acceleration samples are produced. The default value is 0 which corresponds to a data-rate of 100Hz. By changing the content of DR to "1" the selected data-rate will be set equal to 400Hz. PD bit allows to turn on the turn the device out of power-down mode. The device is in powerdown mode when PD= "0" (default value after boot). The device is in normal mode when PD is set to 1. STP, STM bit is used to activate the self test function. When the bit is set to one, an output change will occur to the device outputs (refer to table 2 and 3 for specification) thus allowing to check the functionality of the whole measurement chain. Zen bit enables the generation of DataReady signal for Z-axis measurement channel when set to 1. The default value is 1.
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Register description
LIS302DL
Yen bit enables the generation of DataReady signal for Y-axis measurement channel when set to 1. The default value is 1. Xen bit enables the generation of DataReady signal for X-axis measurement channel when set to 1. The default value is 1.
7.3
CTRL_REG2 (21h)
SIM BOOT -FDS HP_FF_W HP_FF_W HP_coe_ff HP_coe_ff U2 U1 2 1
SIM BOOT FDS HP FF_WU2 HP FF_WU1 HP coeff2 HP coeff1
SPI Serial Interface Mode selection. Default value: 0 (0: 4-wire interface; 1: 3-wire interface) Reboot memory content. Default value: 0 (0: normal mode; 1: reboot memory content) Filtered Data Selection. Default value: 0 (0: internal filter bypassed; 1: data from internal filter sent to output register) High Pass filter enabled for FreeFall/WakeUp # 2. Default value: 0 (0: filter bypassed; 1: filter enabled) High Pass filter enabled for Free-Fall/Wake-Up #1. Default value: 0 (0: filter bypassed; 1: filter enabled) High pass filter cut-off frequency configuration. Default value: 00 (See table below
SIM bit selects the SPI Serial Interface Mode. When SIM is `0' (default value) the 4-wire interface mode is selected. The data coming from the device are sent to SDO pad. In 3-wire interface mode output data are sent to SDA_SDI pad. BOOT bit is used to refresh the content of internal registers stored in the flash memory block. At the device power up the content of the flash memory block is transferred to the internal registers related to trimming functions to permit a good behavior of the device itself. If for any reason the content of trimming registers was changed it is sufficient to use this bit to restore correct values. When BOOT bit is set to `1' the content of internal flash is copied inside corresponding internal registers and it is used to calibrate the device. These values are factory trimmed and they are different for every accelerometer. They permit a good behavior of the device and normally they have not to be changed. At the end of the boot process the BOOT bit is set again to `0'. FDS bit enables (FDS=1) or bypass (FDS=0) the high pass filter in the signal chain of the sensor HP_coeff[2:1]. These bits are used to configure high-pass filter cut-off frequency ft.
ft (Hz) (DR=100 Hz) 2 1 0.5 0.25 ft (Hz) (DR=400 Hz) 8 4 2 1
HPcoeff2,1 00 01 10 11
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LIS302DL
Register description
7.4
CTRL_REG3 [Interrupt CTRL register] (22h)
IHL IHL PP_OD I2CFG2 I2CFG1 I2CFG0 I1CFG2 I1CFG1 I1CFG0 PP_OD I2CFG2 I2CFG1 I2CFG0 I1CFG2 I1CFG1 I1CFG0
Interrupt active high, low. Default value 0. (0: active high; 1: active low) Push-pull/Open Drain selection on interrupt pad. Default value 0. (0: push-pull; 1: open drain) Data Signal on Int2 pad control bits. Default value 000. (see table below) Data Signal on Int1 pad control bits. Default value 000. (see table below)
I1(2)_CFG2 0 0 0 0 1 1
I1(2)_CFG1 0 0 1 1 0 1
I1(2)_CFG0 0 1 0 1 0 1
Int1(2) Pad GND FF_WU_1 FF_WU_2 FF_WU_1 or FF_WU_2 Dataready Not Used
7.5
HP_FILTER_RESET (23h)
Dummy register. Reading at this address zeroes instantaneously the content of the internal high pass-filter. Read data is not significant.
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Register description
LIS302DL
7.6
STATUS_REG (27h)
ZXYOR ZOR YOR XOR ZYXDA ZDA YDA XDA
ZYXOR
X, Y and Z axis Data Overrun. Default value: 0 (0: no overrun has occurred; 1: new data has over written the previous one before it was read) Z axis Data Overrun. Default value: 0 (0: no overrun has occurred; 1: a new data for the Z-axis has overwritten the previous one) Y axis Data Overrun. Default value: 0 (0: no overrun has occurred; 1: a new data for the Y-axis has overwritten the previous one) X axis Data Overrun. Default value: 0 (0: no overrun has occurred; 1: a new data for the X-axis has overwritten the previous one) X, Y and Z axis new Data Available. Default value: 0 (0: a new set of data is not yet available; 1: a new set of data is available) Z axis new Data Available. Default value: 0 (0: a new data for the Z-axis is not yet available; 1: a new data for the Z-axis is available) Y axis new Data Available. Default value: 0 (0: a new data for the Y-axis is not yet available; 1: a new data for the Y-axis is available) X axis new Data Available. Default value: 0 (0: a new data for the X-axis is not yet available; 1: a new data for the X-axis is available)
ZOR
YOR
XOR ZYXDA ZDA
YDA
XDA
7.7
OUT_X (29h)
XD7 XD6 XD5 XD4 XD3 XD2 XD1 XD0
X axis output data.
7.8
OUT_Y (2Bh)
YD7 YD6 YD5 YD4 YD3 YD2 YD1 YD0
Y axis output data.
7.9
OUT_Z (2Dh)
ZD7 ZD6 ZD5 ZD4 ZD3 ZD2 ZD1 ZD0
Z axis output data.
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LIS302DL
Register description
7.10
FF_WU_CFG_1 (30h)
AOI LIR ZHIE ZLIE YHIE YLIE XHIE XLIE
AOI
And/Or combination of Interrupt events. Default value: 0 (0: OR combination of interrupt events; 1: AND combination of interrupt events) Latch Interrupt request into FF_WU_SRC reg with the FF_WU_SRC reg cleared by reading FF_WU_SRC_1 reg. Default value: 0 (0: interrupt request not latched; 1: interrupt request latched) Enable interrupt generation on Z high event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) Enable interrupt generation on Z low event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold) Enable interrupt generation on Y high event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) Enable interrupt generation on Y low event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold) Enable interrupt generation on X high event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) Enable interrupt generation on X low event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold)
LIR
ZHIE
ZLIE
YHIE
YLIE
XHIE
XLIE
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Register description
LIS302DL
7.11
FF_WU_SRC_1 (31h)
X IA ZH ZL YH YL XH XL
IA ZH ZL YH YL XH XL
Interrupt Active. Default value: 0 (0: no interrupt has been generated; 1: one ore more interrupt has been generated) Z High. Default value: 0 (0: no interrupt, 1: ZH event has occurred) Z Low. Default value: 0 (0: no interrupt; 1: ZL event has occurred) Y High. Default value: 0 (0: no interrupt, 1: YH event has occurred) Y Low. Default value: 0 (0: no interrupt, 1: YL event has occurred) X High. Default value: 0 (0: no interrupt, 1: XH event has occurred) X Low. Default value: 0 (0: no interrupt, 1: XL event has occurred)
Free-fall and wake-up source register. Read only register. Reading at this address clears FF_WU_SRC_1 register and the FF, WU 1 interrupt and allows the refreshment of data in the FF_WU_SRC_1 register if the latched option was chosen.
7.12
FF_WU_THS_1 (32h)
DCRM THS6 THS5 THS4 THS3 THS2 THS1 THS0
DCRM THS6, THS0
Resetting mode selection. Default value: 0 (0: counter resetted; 1: counter decremented) Free-fall / wake-up Threshold: default value: 000 0000
Most significant bit (DCRM) is used to select the resetting mode of the duration counter. If DCRM=0 counter is resetted when the interrupt is no more active else if DCRM=1 duration counter is decremented.
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LIS302DL
Register description
7.13
FF_WU_DURATION_1 (33h)
D7 D7-D0 D6 D5 D4 D3 D2 D1 D0
Duration value. Default value: 0000 0000
Duration register for Free-Fall/Wake-Up interrupt 1. Duration step and maximum value depend on the ODR chosen. Step 2.5 msec, from 0 to 637.5 msec if ODR=400Hz, else step 10 msec, from 0 to 2.55 sec when ODR=100Hz. The counter used to implement duration function is blocked when LIR=1 in configuration register and the interrupt event is verified
7.14
FF_WU_CFG_2 (34h)
AOI AOI LIR LIR ZHIE ZLIE YHIE YLIE XHIE XLIE
And/Or combination of Interrupt events. Default value: 0 (0: OR combination of interrupt events; 1: AND combination of interrupt events) Latch Interrupt request into FF_WU_SRC reg with the FF_WU_SRC reg cleared by reading FF_WU_SRC_2 reg. Default value: 0 (0: interrupt request not latched; 1: interrupt request latched) Enable interrupt generation on Z high event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) Enable interrupt generation on Z low event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold) Enable interrupt generation on Y high event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) Enable interrupt generation on Y low event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold) Enable interrupt generation on X high event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) Enable interrupt generation on X low event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold)
ZHIE
ZLIE
YHIE
YLIE
XHIE
XLIE
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Register description
LIS302DL
7.15
FF_WU_SRC_2 (35h)
X IA IA ZH ZL YH YL XH XL
Interrupt Active. Default value: 0 (0: no interrupt has been generated; 1: one or more interrupt event has been generated) Z High. Default value: 0 (0: no interrupt; 1: ZH event has occurred)
ZH
ZL YH YL XH XL
Z Low. Default value: 0 (0: no interrupt; 1: ZL event has occurred) Y High. Default value: 0 (0: no interrupt; 1: YH event has occurred) Y Low. Default value: 0 (0: no interrupt; 1: YL event has occurred) X High. Default value: 0 (0: no interrupt; 1: XH event has occurred) X Low. Default value: 0 (0: no interrupt; 1: XL event has occurred)
Free-fall and wake-up source register. Read only register. Reading at this address clears FF_WU_SRC_2 register and the FF, WU 2 interrupt and allows the refreshment of data in the FF_WU_SRC_2 register if the latched option was chosen.
7.16
FF_WU_THS_2 (36h)
DCRM DCRM THS6, THS0 THS6 THS5 THS4 THS3 THS2 THS1 THS0
Resetting mode selection. Default value: 0 (0: counter resetted; 1: counter decremented) Free-fall / wake-up Threshold. Default value: 000 0000
Most significant bit (DCRM) is used to select the resetting mode of the duration counter. If DCRM=0 counter is resetted when the interrupt is no more active else if DCRM=1 duration counter is decremented.
7.17
FF_WU_DURATION_2 (37h)
D7 D6 D5 D4 D3 D2 D1 D0
D7-D0
Duration value. Default value: 0000 0000
Duration register for Free-Fall/Wake-Up interrupt 2. Duration step and maximum value depend on the ODR chosen. Step 2.5 msec, from 0 to 637.5 msec if ODR=400Hz, else step 10 msec, from 0 to 2.55 sec when ODR=100Hz. The counter used to implement duration function is blocked when LIR=1 in configuration register and the interrupt event is verified.
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LIS302DL
Package information
8
Package information
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 10. LGA 14: Mechanical Data & Package Dimensions
mm DIM. MIN. A1 A2 A3 D1 E1 e d L1 N N1 P1 P2 T1 T2 R h k i s 0.965 0.640 0.750 0.450 1.200 0.150 0.050 0.100 0.100 0.180 2.850 4.850 0.220 3.000 5.000 0.800 0.300 4.000 1.360 1.200 0.975 0.650 0.800 0.500 TYP. 0.920 MAX. 1.000 0.700 MIN. TYP. MAX. 0.0362 0.0394 0.0275 inch
OUTLINE AND MECHANICAL DATA
0.260 0.0071 0.0087 0.0102 3.150 0.1122 0.1181 0.1240 5.150 0.1909 0.1968 0.2027 0.0315 0.0118 0.1575 0.0535 0.0472 0.985 0.0380 0.0384 0.0386 0.660 0.0252 0.0256 0.0260 0.850 0.0295 0.0315 0.0335 0.550 0.0177 0.0197 0.0217 1.600 0.0472 0.0059 0.0020 0.0039 0.0039 0.0630
LGA14 (3x5x0.92mm) Pitch 0.8mm Land Grid Array Package
7773587 C
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Revision history
LIS302DL
9
Revision history
Table 8.
Date 03-Oct-2006
Document revision history
Revision 1 Initial release. Changes
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LIS302DL
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